; Generate clock and chip enable signals to operate 
; 1 MAX195 A/D converter
; 2 MAX542 D/A converters
; connected to 56002 SSI in network mode.
; 
; Copyright (C) 1999,2000 Juergen Mueller (juergen@e-basteln.de)
; 
; Check TSOUT timing of CS4215!
; (TSOUT is sampled on rising edge of SCLK, assuming it will lag behind SCLK).
; 
; jm  6.9.1998 	original version
; jm 16.1.2000	tried to speed up conversion cycle: 
; 					2nd MAX542 (Z out) moved from slot 5 (CS2) to slot 7 (CS4)

CHIP	STM_ADDA2	GAL22V10

; Inputs:
; CLK = SCLK  	SSI SCLK (from CS4215)
; TS		SSI TSOUT (from CS4215)
; /RESET	system reset (from 56002)

; Outputs:
; C1		SCLK/4, for MAX195 conversion CLK
; ISCLK		inverted SCLK, for MAX 542 SCLK
; /CS1		enable MAX195, first MAX542
; /CS4		enable second MAX542
; /CONV		start of conversion for MAX195

#define ACTIVE (CS1 + CS2 + CS3 + CS4)
#define ZERO (/D3 * /D2 * /C1 * /C0)
#define NOZERO (D3 + D2 + C1 + C0)

CLK	SCLK	TS	/RESET	NC	NC	NC	NC	NC
NC	NC	GND
NC	C0	C1	/CS2	/CS3	D2	D3	/CS1	/CS4
/CONV	ISCLK	VCC

AR	=	RESET		; asynchronous reset
ISCLK	=	/SCLK		; inverted SCLK for MAX542

; slow MAX195 CLK runs continuously.
; CLK is synchronized with TS so it can replace D0,D1.
C0	:=	TS + /C0
C1	:=	/TS * (C0*/C1 + /C0*C1)

; All enable signals triggered by TS (time slot).
; Idle state has CS1, CS2, CONV high.

D2 	:= 	ACTIVE * (/D2*C1*C0 + D2*(/C1+/C0)) 
D3	:=	ACTIVE * (/D3*D2*C1*C0 + D3*(/D2+/C1+/C0))

CS1	:=	TS + CS1 * NOZERO
CS2	:=	CS1 * ZERO + CS2 * NOZERO
CS3	:=	CS2 * ZERO + CS3 * NOZERO
CS4	:=	CS3 * ZERO + CS4 * NOZERO

; /CONV signal triggered in CS4 cycle.
; /CONV may change phase only while C1 is low!

CONV	:= 	CS4 * D2 * /D3 * /C1 + CONV * C1